Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.3.3. Kernel Driver Information

MCDMA kernel module identifies the device based on vendor ID and device ID using the Linux PCI framework and does BAR mapping. It creates the character device node associated with the physical function.

Kernel Driver currently supports 4 Physical Functions Simultaneously, each PF supporting upto 256 channels. For AVST up to 256 channels per PF are supported in the Intel® Quartus® Prime 21.3 release. For AVMM, up to 512 channels per PF are supported in the Intel® Quartus® Prime 21.3 release.

The character device node is used by the application to access the PF device. It supports the following operations:
  • Device Management:
    • IP Reset
    • open & close
    • read & write
    • readv & writev
  • Channel Management:
    • Descriptor Ring Mangement
  • Completions Management:
    • Interrupt Mode
    • Poll Mode

Did you find the information on this page useful?

Characters remaining:

Feedback Message