Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.1.2.1. D2H Descriptor Fetch

When you enable multiple channels over single port in AVST mode, the MCDMA IP limits the number of the channels that can be active or can prefetch the descriptors for the data movement to avoid implementing the larger memory to hold descriptors simultaneously for all channels.

The descriptor FIFO is designed to hold descriptors only for a defined number of channels. When the data is received on the user interface (AVST port), there is no handshake between Host SW and User Logic through the MCDMA IP to control the order of descriptor fetch or data movement of multiple channels. To enable easy access to descriptors of multiple channels, the MCDMA IP implements segmentation of descriptor FIFO.

Below are the two IP parameters defined to provide user programmability.
  • D2H Prefetch Channels: D2H descriptor memory is arranged in multiple segments to support user selectable number of prefetch queues (also known as Active Queues).
  • Maximum Descriptor Fetch: Maximum number of D2H descriptors that can be fetched for each prefetch channel.

Since the MCDMA IP only implements N-prefetch channels, it is capable of handling user AVST data received for a non-prefetched channel. When D2H data mover receives data on AVST for a channel that does not have descriptors prefetched, D2HDM requests for descriptors to be fetched for that channel.

When all the segments are occupied and D2HDM receives data for a channel that does not have descriptors prefetched, the least recently used segment IS cleared to accommodate descriptors fetched for this new channel. Descriptors in the least recently used segment that were cleared, are refetched whenever D2HDM receives data for the corresponding channel.

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