Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022

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Document Table of Contents Eye Viewer

The P-Tile Debug Toolkit supports the Eye Viewer tool that allows you to plot the eye diagram for each channel. The Eye Viewer tool:
  • Provides a pictorial representation of the eye for each channel, both in the bifurcated (e.g., x8x8) and non-bifurcated (e.g., x16) configurations.
  • Provides information on the total eye height, total eye width and eye measurement information from the center of the eye to the four corners (left, right, top, bottom).
  • Uses fixed step sizes in the horizontal and vertical directions.
  • Performs the eye measurement at the following bit error rates (BER):
    • 8.0 GT/s (Gen3) @ e-8, 100% confidence level
    • 16.0 GT/s (Gen4) @ e-9, 90% confidence level
Note: The P-Tile Avalon Streaming Intel FPGA IP for PCI Express Eye Viewer feature of the Debug Toolkit does not support independent error sampler for performing eye margining. The eye margining is performed on the actual data path. As a result, the eye margining may produce uncorrectable errors in the data stream and cause the LTSSM to go to the Recovery state. You may mask out all errors (example AER registers) while performing the eye margining and reset all error counters, error registers etc. after margining is completed.
  1. In the System Console Tools menu option, click on Eye View Tool.
    Figure 59. Opening the Eye Viewer
  2. This will open a new tab Eye View Tool next to the Main View tab. Choose the instance and channel for which you want to run the eye view tests.
    Figure 60. Opening the Instance and Channel
  3. The messages window displays information messages to indicate the eye view tool's progress.
    Figure 61. Eye View Tool Messages
  4. Once the eye plot is complete, the eye height, eye width and eye diagram are displayed.
    Figure 62. Sample Eye Plot