Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.8.1.2. H2D Descriptor Completion Packet Format (h2ddm_desc_cmpl)

The H2D DM descriptor completion data which is the returned completion from the host when original descriptor request was with MM_Mode=0 is as follows.

Table 26.  H2D Descriptor Completion Packet Format
Name Width Description
CMPL_LEN [13:0] 14

Length of the completion in bytes.

Completion data are returned from next cycle until the end of packet when the EOP is asserted.

LOWER_ADDR [37:14] 24

The lower address indicates lower 24 bits of starting byte address in current completion corresponding to first completion only.

RSVD 1

Reserved

DM_FmtType [46:39] 8

‘h4A: DMCmpl

PFVF [62:47] 16

{VF_ACTIVE, VFNUM[10:0], PF[3:0]} copied from original request.

Cmpl_sts [65:63] 3

3’b000: Success

3’b001: Not Successful.

All other values are reserved.

DESC_IDX1 [81:66] 16

Unique Identifier for each descriptor. This is the same ID copied from original request.

En_partial_cmpl_data [82:82] 1
Note: This parameter is not supported in the Intel® Quartus® Prime 22.1 release.
DESC_IDX2 [94:83] 12

AVST completion DESC_IDX2 value which is copied from original request.

RSVD [255:95] 161

Reserved

Completion data 256b / 512b
Note: This parameter is not supported in the Intel® Quartus® Prime 22.1 release.

Partial completion data (En_Partial_cmpl_data=1)

Note: This is Param based data width

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