Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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9.3. Control Register (GCSR)

This space contains global control/status registers that control the DMA operation. Access to this register set is restricted to PF0 only.

Table 155.  Control Register
Register Name Address Offset Access Type Description
CTRL 8’h00 R/W Reserved
RESERVED 8’h04 Reserved
WB_INTR_DELAY 8’h08 R/W Delay the writeback and/or the MSI-X interrupt until the time elapsed from a prior writeback/interrupt exceeds the delay value in this register.
RESERVED 8’h0C – 8’h6F Reserved
VER_NUM 8’h70 RO Multi Channel DMA IP for PCI Express version number
SW_RESET 9'h120 RW

Write this register to issue Multi Channel DMA IP reset without disturbing PCI Express link. This resets all queues and erase all the context. Can be issued only from PF0.

Table 156.   CTRL (Offset 8’h0)
Bit [31:0] Name R/W Default Description
[31:0] rsvd Reserved
Table 157.   WB_INTR_DELAY (Offset 8’h08)
Bit [31:0] Name R/W Default Description
[31:20] rsvd Reserved
[19:0] wb_intr_delay R/W 0 Delay the writeback and/or the MSI-X interrupt until the time elapsed from a prior writeback/interrupt exceeds the delay value in this register. Each unit is 2ns.
Table 158.   VER_NUM (Offset 9’h070)
Bit [31:0] Name R/W Default Description
[31:24] rsvd RESERVED
[23:16] MAJOR_VER RO 0

Major version number of Multi Channel DMA IP for PCI Express

[15:8] UPDATE_VER RO 0 Update version number of Multi Channel DMA IP for PCI Express
[7:0] PATCH_VER RO 0 Patch version number of Multi Channel DMA IP for PCI Express

IP version number is defined using MAJOR_VER.UPDATE_VER.PATCH_VER format. For information about MCDMA IP version number, refer to the IP Revision History.

Table 159.   SW_RESET (Offset 9'h120)
Bit [31:0] Name R/W Default Deacription
[31:1] rsvd     Reserved
[0] SW_RESET RW 0

Set this bit to issue MCDMA IP reset without disturbing PCIe link. This resets all queues and erases all the context. Issued only from PF0.

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