3.8. Data Mover Only
The figure below is the top-level block diagram of the MCDMA IP in Data Mover Only mode with user descriptor controller.
- HIP Interface: Adapts to various PCIe HIP variants (P-/F-Tile) the Data Mover subsystem is interfacing to.
- Host to Device (H2D) Data Mover: Provides AVST source and sink interfaces to external descriptor controller for both descriptor fetch and data move operations
- Device to Host (D2H) Data Mover: Provides AVST source and sink interfaces to external descriptor controller to initiate data move operations and to send writeback/interrupt.
- Bursting Avalon Master (BAM): Performs non-bursting PIO operations for register programming.
- Support for PCIe semantics
- Scheduler enforces PCIe ordering rules in both Tx and Rx direction leading to PCIe HIP
- TLP chunking at MPS size
- Check for the 4KB cross over and other error logging
- Completion re-ordering: Data Mover subsystem performs the re-ordering of the received completions before sending data to AVMM Write Master or sending the descriptor completion packets to external descriptor controller.
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