Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.8. Data Mover Only

Data Mover Only mode is one of the MCDMA IP user modes for Endpoint MCDMA P-Tile and F-Tile IPs in Intel® Quartus® Prime 22.1. This mode supports external descriptor fetch based on external descriptor controller. In this mode, the MCDMA IP core becomes a PCIe Data Mover subsystem implementing the usual PCIe semantics, but it does not have any blocks related to DMA descriptor functionality.
Note: Data Mover with the External Descriptor Controller only supports data movement over AVMM interface to the user logic. AVST inteface support to user logic may be added in future.

The figure below is the top-level block diagram of the MCDMA IP in Data Mover Only mode with user descriptor controller.

Figure 12. PCIe Data Mover Subsystem connected to External DMA Controller
Data mover subsystem supports the following functionality:
  • HIP Interface: Adapts to various PCIe HIP variants (P-/F-Tile) the Data Mover subsystem is interfacing to.
  • Host to Device (H2D) Data Mover: Provides AVST source and sink interfaces to external descriptor controller for both descriptor fetch and data move operations
  • Device to Host (D2H) Data Mover: Provides AVST source and sink interfaces to external descriptor controller to initiate data move operations and to send writeback/interrupt.
  • Bursting Avalon Master (BAM): Performs non-bursting PIO operations for register programming.
  • Support for PCIe semantics
    • Scheduler enforces PCIe ordering rules in both Tx and Rx direction leading to PCIe HIP
    • TLP chunking at MPS size
    • Check for the 4KB cross over and other error logging
  • Completion re-ordering: Data Mover subsystem performs the re-ordering of the received completions before sending data to AVMM Write Master or sending the descriptor completion packets to external descriptor controller.

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