|Signal Name||I/O Type||Description|
|pin_perst_n||Input||This is an active-low input to the PCIe Hard IP, and implements the PERST# function defined by the PCIe specification.|
|npor||Input||Application drives this active-low reset input to the PCIe Hard IP. This resets entire PCIe Hard IP. If not used, you must tie this input to 1.|
This is an active low reset status. This is deasserted after the PCIe Hard IP has come out of reset.
This is an active low input signal. A "1" indicates that the FPGA device is not yet fully configured.
A "0" indicates the device has been configured and is in normal operating mode.
To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output. The Reset Release IP is required in Intel Stratix 10 design. It holds the Multi Channel DMA for PCI Express IP in reset until the FPGA is fully configured and has entered user mode.
|P-Tile and F-Tile|
|pin_perst_n||Input||See H-Tile pin_perst description|
|ninit_done||Input||See H-Tile ninit_done description|
Resets MCDMA soft IP blocks and user logic. app_rst_n is asserted when software writes to SW_RESET register bit.
|p0_pld_link_req_rst_o||Output||Warm reset request to application|
|p0_pld_warm_rst_rdy_i||Input||Warm reset ready from application|
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