Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 8/19/2022
Public

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3.8.3. Application Specific Bits

Table 31.  Application Specific Bits
Bit [2] Bit [1] Bit [0] Description
0 1 1

Reserved

0 1 0

Reserved

0 0 1

Data mover considers this as WB and picks the address/data from AVST sink interface in D2H direction (d2hdm_desc).

Not applicable for H2D, and external DMA controller must drive 0.

0 0 0

Reserved

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