Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.4.2.1. Export the Root Partition with SLD JTAG Bridge

To export a reusable root partition with SLD JTAG Bridge that allows debugging of core partitions in another project, follow these steps.
  1. Create a reserved core partition and define a Logic Lock region.
  2. Generate and instantiate SLD JTAG Bridge Agent in the root partition.
    The combination of agent and host allows debugging the reserved core partition in Consumer projects.
  3. Generate and instantiate the SLD JTAG Bridge Host in the reserved core partition.
  4. Add a Signal Tap instance to the root partition, as Step 1: Add the Signal Tap Logic Analyzer to the Project describes.
  5. In the Signal Tap instance, specify the signals for monitoring. This action allows debugging the root partition in the Developer and Consumer projects.
  6. Compile the design and Signal Tap instance.
  7. Click Project > Export Design Partition. By default, the .qdb file you export includes any Signal Tap HDL instances for the partition.
  8. Manually copy files to the project that reuses the root partition:
    • In designs targeting the Intel® Arria® 10 device family, copy .qdb and .sdc files.
    • In designs targeting the Intel® Stratix® 10 device family copy the .qdb file.
    In designs with multiple child partitions, you must provide the hierarchy path and the associated index of the JTAG Bridge Instance Agents in the design to the Consumer.

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