Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.4.1.4.1. Debug a Core Partition Exported with Signal Tap HDL Instances2.9.4.1.6. Debug a Core Partition Exported with Signal Tap HDL Instances

To use Signal Tap to debug a design that includes a core partition exported with Signal Tap HDL instances, follow these steps:
  1. Add to your project the black-box file that you create in Export a Core Partition with Signal Tap HDL Instances.
  2. To create a design partition, click Assignments > Design Partitions Window. Define a partition and assign the exported partition .qdb file as the Partition Database File option.
  3. Create a Signal Tap file for the top-level partition as Step 1: Add the Signal Tap Logic Analyzer to the Project describes.
  4. Compile the design and Signal Tap instances.
  5. Generate a Signal Tap file for the reused Core Partition with the File > Create/Update > Create Signal Tap File from Design Instance command.
  6. Program the Intel FPGA device with the design and Signal Tap instances.
  7. Perform hardware verification of top-level partition with the Signal Tap instance defined in Step 3.
  8. Perform hardware verification of the Reused Core Partition with the Signal Tap instance defined in Step 5.

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