Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.4.1.2. Debug a Core Partition through Partition Boundary Ports

To use Signal Tap to debug a design that includes a core partition exported with partition boundary ports from another project, follow these steps:
  1. Add to your project the black-box file that you create in Export a Core Partition with Partition Boundary Ports.
  2. To run synthesis, double-click Analysis & Synthesis on the Compilation Dashboard.
  3. Define a Signal Tap instance with the Signal Tap GUI, or by instantiating a Signal Tap HDL instance in the top level root partition, as Step 1: Add the Signal Tap Logic Analyzer to the Project describes.
  4. Connect the partition boundary ports of the reused core partition to the HDL instance, or add post-synthesis or post-fit nodes to the Signal Configuration tab in the Signal Tap logic analyzer GUI.
  5. To create a design partition, click Assignments > Design Partitions Window. Define a partition and assign the exported partition .qdb file as the Partition Database File option.
  6. Compile the design, including all partitions and the Signal Tap instance.
  7. Program the Intel FPGA device with the design and Signal Tap instances.
  8. Perform data acquisition with the Signal Tap logic analyzer GUI.

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