22.214.171.124. Signal Tap Debugging with a Root Partition
You implement the debug bridge with the SLD JTAG Bridge Agent Intel® FPGA IP and SLD JTAG Bridge Host Intel® FPGA IP pair for each reserved core boundary in the design. You instantiate the SLD JTAG Bridge Agent IP in the root partition, and the SLD JTAG Bridge Host IP in the core partition.
For details about the debug bridge, refer to the SLD JTAG Bridge in the System Debugging Tools Overview chapter.
Did you find the information on this page useful?