Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.4.1.5. Export a Core Partition with Signal Tap HDL Instances

To export a core partition with Signal Tap HDL instances for reuse and eventual Signal Tap debugging in another project, follow these steps:
  1. To run synthesis, double-click Analysis & Synthesis on the Compilation Dashboard.
  2. Define a design partition for reuse that contains only core logic. Click Assignments > Design Partitions Window to define the partition.
  3. Add a Signal Tap HDL instance to the core partition, connecting it to nodes of interest.
  4. Click Project > Export Design Partition. By default, the .qdb file you export includes any Signal Tap HDL instances for the partition.
  5. Create a black box file that defines only the port and module or entity definitions, without any logic.
  6. Manually copy the exported partition .qdb file and any black box file to the other project.

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