Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.9.4.1.3. Export a Core Partition with Partition Boundary Ports

To export a core partition with partition boundary ports for reuse and Signal Tap debugging in another project, follow these steps:
  1. To run synthesis, double-click Analysis & Synthesis on the Compilation Dashboard.
  2. Define a design partition for reuse that contains only core logic. Click Assignments > Design Partitions Window to define the partition.
  3. To create partition boundary ports for the core partition, specify the Create Partition Boundary Ports assignment in the Assignment Editor for partition ports.
  4. Click Project > Export Design Partition. By default, the .qdb file you export includes any Signal Tap HDL instances for the partition.
  5. Compile the design and Signal Tap instance.
  6. Create a black box file that defines only the port and module or entity definitions, without any logic.
  7. Manually copy the exported partition .qdb file and any black box file to the other project.

Optionally, you can verify signals in the root and core partitions in the Developer project with the Signal Tap logic analyzer.

Did you find the information on this page useful?

Characters remaining:

Feedback Message