184.108.40.206.3. Export a Core Partition with Partition Boundary Ports
- To run synthesis, double-click Analysis & Synthesis on the Compilation Dashboard.
- Define a design partition for reuse that contains only core logic. Click Assignments > Design Partitions Window to define the partition.
- To create partition boundary ports for the core partition, specify the Create Partition Boundary Ports assignment in the Assignment Editor for partition ports.
- Click Project > Export Design Partition. By default, the .qdb file you export includes any Signal Tap HDL instances for the partition.
- Compile the design and Signal Tap instance.
- Create a black box file that defines only the port and module or entity definitions, without any logic.
- Manually copy the exported partition .qdb file and any black box file to the other project.
Optionally, you can verify signals in the root and core partitions in the Developer project with the Signal Tap logic analyzer.
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