Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.1.2. Create Simulation Testbench Dialog Box Settings

The following options are available for RTL simulation testbench generation from the Signal Tap Create Simulation Testbench Dialog Box. The default values derive from Signal Tap signal data.
Table 23.  Create Simulation Testbench Dialog Box (Signal Tap Logic Analyzer)
Name Description
Directory Specifies the directory to generated save RTL simulation testbench files.
Note: Signal Tap currently supports testbench generation only within the current project directory.
Starting hierarchy to simulate Specifies the design hierarchy level to include in the simulation. The default location is a subdirectory of the project with the hierarchy name.
Testbench top level properties Specifies the following testbench properties. By default, these values populate from the Signal Tap data:
  • Module name—specifies the name of the design module that you want to simulate, as specified in Signal Tap
  • DUT instance name—specifies the default instance name for the design under test (DUT) in your simulator. The default is DUT. This name appears in your simulator.
  • DUT clock port name—specifies the clock port name of the design under test (DUT) for simulation. Signal Tap automatically derives this value based on the DUT instance name.
Simulation event properties Specifies the following testbench properties. By default, these values populate from the Signal Tap data:
  • Initial unknown data—specifies the number of clock cycles for which the data value is initially unknown at the start of simulation.
  • Discontinued data due to storage qualification—specifies the number of clock cycles for which the data is discontinued because of lack of storage.
  • Final unknown data—specifies the number of clock cycles for which the data is unknown initially at the end of simulation.
Options The following options must be enabled for testbench generation:
  • Use force statement based on value change—specifies the number of clock cycles for which the data value is initially unknown at the start of simulation.
    Note: Signal Tap uses a Verilog HDL force statement to inject the Signal Tap data into the simulator.
  • Generate simulation scripts—specifies that simulation scripts generate in vendor specific subdirectories during testbench generation. Source these scripts in your simulator to setup simulation.
Node string replacement Specifies options for nomenclature and syntax within the generated testbench:
  • Prefix hierarchies with instance name—specifies the instance name that prepends to hierarchy names in the testbench. In general, the derived default value is suitable.
  • Search|Replace—specifies the search and replace strings for Node string replacement.
Preview Displays the result of the Node string replacement settings within the testbench.

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