220.127.116.11.2. Preparing the Base Revision for Signal Tap Debugging
In the base revision, for each PR region that you want to debug in the design:
- Instantiate the SLD JTAG Bridge Agent Intel® FPGA IP in the static region.
- Instantiate the SLD JTAG Bridge Host Intel® FPGA IP in the PR region of the default persona.
You can use the IP Catalog or Platform Designer to instantiate SLD JTAG Bridge components.
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