Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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7.7.2. High Level Flow

  1. Install the DSP Builder for Intel® FPGAs software, so you have the necessary libraries to enable this flow
  2. Build the design using Simulink and the DSP Builder for Intel® FPGAs libraries.
    DSP Builder for Intel® FPGAs helps to convert the Simulink design to HDL
  3. Include Avalon® memory mapped components in the design (DSP Builder for Intel® FPGAs can port non- Avalon® memory mapped components)
  4. Include Signals and Control blocks in the design
  5. Separate synthesizable and non-synthesizable logic with boundary blocks.
  6. Integrate the DSP system in Platform Designer
  7. Program the Intel FPGA
  8. Interact with the Intel FPGA through the supported MATLAB* API commands.

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