Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 10/13/2021
Public

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2.9.3. Debugging Partial Reconfiguration Designs with Signal Tap

You can debug a Partial Reconfiguration (PR) design with the Signal Tap logic analyzer. The Signal Tap logic analyzer supports data acquisition in the static and PR regions. You can debug multiple personas present in a PR region and multiple PR regions.

For examples on debugging PR designs targeting specific devices, refer to AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design or AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design .

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