Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021

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3.2.3. Transmitter Channel-to-Channel Skew

The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an important parameter based on the Intel® Stratix® 10 transmitter in a source-synchronous differential interface:

  • TCCS is the difference between the fastest and slowest data output transitions, including the TCO variation and clock skew.
  • For LVDS transmitters, the Timing Analyzer provides the TCCS value in the TCCS report (report_TCCS) in the Intel® Quartus® Prime compilation report, which shows TCCS values for serial output ports.
  • You can also get the TCCS value from the device datasheet.

For Intel® Stratix® 10 devices, perform PCB trace compensation to adjust the trace length of each LVDS channel to improve channel-to-channel skew when interfacing with non-DPA receivers at data rate above 840 Mbps. The Intel® Quartus® Prime software Fitter Report panel reports the amount of delay you must add to each trace for the Intel® Stratix® 10 device. You can use the recommended trace delay numbers shown under the LVDS Transmitter/Receiver Package Skew Compensation panel and manually compensate the skew on the PCB board trace to reduce channel-to-channel skew, thus meeting the timing budget between LVDS channels.

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