Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

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3.1.7. LVDS Interface with External PLL Mode

The LVDS SERDES IP core parameter editor provides an option for implementing the LVDS interface with the Use External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings.

If you enable the Use External PLL option with the LVDS SERDES IP core transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:

  • Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP core transmitter and receiver
  • Load enable to the SERDES of the LVDS SERDES IP core transmitter and receiver
  • Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
  • Asynchronous PLL reset port of the LVDS SERDES IP core receiver
  • PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP core receiver

The Clock Resource Summary tab in the LVDS SERDES IP core parameter editor provides the details for the signals in the preceding list.

You must instantiate an IOPLL IP core to generate the various clocks and load enable signals. You must configure these settings in IOPLL IP core parameter editor:

  • LVDS External PLL options in the Settings tab
  • Output Clocks options in the PLL tab
  • Compensation Mode option in the PLL tab
Table 9.  Compensation Mode Setting to Generate IOPLL IP CoreWhen you generate the IOPLL IP core, use the PLL setting in this table for the corresponding LVDS functional mode.
LVDS Functional Mode IOPLL IP Core Setting
TX, RX DPA, RX Soft-CDR Direct mode
RX non-DPA LVDS compensation mode
Note: If you are using an external PLL for a wide transmitter interface that spans multiple I/O banks, only the second pair of clocks (indexed by "[1]") from the external PLL is valid.

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