Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021

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4.3. LVDS SERDES IP Core Timing

Use the Intel® Quartus® Prime software to generate the required timing constraint to perform proper timing analysis of the LVDS SERDES IP core in Intel® Stratix® 10 devices.
Table 21.   LVDS SERDES IP Core Timing Components
Timing Component Description
Source Synchronous Paths The source synchronous paths are paths where clock and data signals are passed from the transmitting devices to the receiving devices. For example:
  • FPGA/LVDS/TX to external receiving device transmitting
  • External transmitting device to FPGA/non-DPA mode/LVDS/RX receiving path
Dynamic Phase Alignment Paths A DPA block registers the I/O capture paths in soft-CDR and DPA-FIFO modes. The DPA block dynamically chooses the best phase from the PLL VCO clocks to latch the input data.
Internal FPGA Paths

The internal FPGA paths are the paths inside the FPGA fabric:

  • LVDS RX hardware to core registers paths
  • Core registers to LVDS TX hardware paths
  • Others core registers to core registers path

The Timing Analyzer reports the corresponding timing margins.

Table 22.   LVDS SERDES Timing Constraint FilesThis table lists the timing files generated by the LVDS SERDES IP core. Use these files for successful timing analysis of the LVDS SERDES IP core. You can find these files in the <variation_name> directory.
File Name Description

This .sdc file allows the Intel® Quartus® Prime Fitter to optimize timing margins with timing-driven compilation. The file also allows the Timing Analyzer to analyze the timing of your design.

The IP core uses the .sdc for the following operations:

  • Creating clocks on PLL inputs
  • Creating generated clocks
  • Calling derive_clock_uncertainty
  • Creating proper multi-cycle constraints

You can locate this file in the .qip generated during IP generation.

sdc_util.tcl This .tcl file is a library of functions and procedures that the .sdc uses.

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