Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.3. Intel® Stratix® 10 GPIO Banks, SERDES, and DPA Locations

The I/O banks are located in I/O columns. Each I/O bank contains its own PLL, dynamic phase alignment (DPA), and SERDES circuitries.
Figure 1. I/O Bank Structure with I/O PLL, DPA, and SERDESThis figure shows an example of I/O banks in one Intel® Stratix® 10 device. The I/O banks availability and locations vary among Intel® Stratix® 10 devices.

Did you find the information on this page useful?

Characters remaining:

Feedback Message