Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.4.1. Aligning Word Boundaries

After initializing the LVDS SERDES IP core in DPA or non-DPA mode, perform these steps to align the word boundaries.
  1. Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the rx_bitslip_reset port.
  2. Begin word alignment by applying pulses as required to the rx_bitslip_ctrl port.

After the word boundaries are established on each channel, the interface is ready for operation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message