||Updated the information about the receiver timing analysis in non-DPA mode.
||Updated the code to add to the .sdc file to specify the RCCS value.
||Added the IP release information.
- Updated the figure showing the I/O bank structure to add the pin naming orientation.
- Updated the section about pin placement for differential channels to add information about sharing the dedicated reference clock input of one I/O bank to clock the PLLs in other I/O banks.
- Updated the figure showing the PLLs driving DPA-enabled differential receiver channels to add example of an invalid PLL configuration.
||Removed the Use clock-pin drive parameter from the LVDS SERDES IP core general settings.
||Updated the figure showing the I/O bank structure:
- Added I/O bank structure for Intel® Stratix® 10 GX 10M device
- For I/O banks figure of other Intel® Stratix® 10 devices:
- Marked only bank 3A as SDM shared LVDS I/O
- Marked HPS shared LVDS I/Os
- Added 3 V I/O banks 7A, 7B, and 7C
- Updated the programmable pre-emphasis diagram to remove the word "peak-peak".
- Added guideline topic about LVDS SERDES limitation for Intel® Stratix® 10 GX 400, SX 400, and TX 400 devices.
||Corrected the clock connection to the register and rx_coreclock in the figure showing the connection for non-DPA or DPA receiver interface with the IOPLL IP core in external PLL mode.
- Moved the LVDS SERDES usage modes summary table into its own topic.
- Updated the description of the LVDS SERDES usage modes table to improve accuracy.
- Updated the table that lists the functional modes of the LVDS SERDES IP core to specify that all functional modes support SERDES factors of 3 to 10.
||Updated the guidelines for the LVDS interface with external PLL mode:
- Combined the figures for the non-DPA and DPA modes.
- Marked in the figures the ports that are available in CPA mode only.
- Updated the source for the LVDS SERDES IP reset signal.
- Updated the connection of the locked signal from the IOPLL IP to the ext_pll_locked port of the LVDS SERDES IP.
||Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard.
- Updated the table listing the dedicated circuitries and features of the differential transmitter to clarify that the serializer width is from 3-bits to 10-bits.
- Updated the guideline about the LVDS reference clock source to include support for reference clock input from other I/O banks.
- Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
- Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
- Removed restriction of using the CPA block while the external PLL option is turned on.
- Updated the topic about the timing analysis for the external PLL mode to improve clarity.
- Updated the topic about the simulation design example to add a note about the non-synthesizable simulation driver.
- Renamed "TimeQuest Timing Analyzer" to "Timing Analyzer".
- Renamed "SignalTap" to "Signal Tap".
- Clarified that all LVDS SERDES IP usage modes support SERDES factors of 3 to 10.
- Clarified that unused pins within an I/O bank with DPA feature enabled can be assigned to single ended or differential I/O standards that has the same VCCIO voltage level used by the bank in Guideline: Pin Placement for Differential Channels section.
- Removed LVDS channels count tables in Intel® Stratix® 10 LVDS Channels Support topic and added link to Intel® Stratix® 10 pin-out files.
- Removed the "pending characterization" labels in the topic showing the example for the RSKM calculation.
- Updated the list of LVDS SERDES IP core features to include the CPA block.
- Updated outclk2 to outclk4 in all examples of using the LVDS interfaces in external PLL mode.
- Updated tables and examples for IOPLL and LVDS SERDES IP cores signals in external PLL mode to include information about using the IP cores with the CPA block turned on.
- Updated the LVDS SERDES IP core instantiation guideline to specify that you can use multiple LVDS SERDES IP cores instance per I/O bank in any functional mode by using an external PLL.
- Corrected typograpical error—changed tx_inclock to rx_inclock—in the topic about the deserializer.
- Updated the figures descriptions in the guideline topic about using external PLL to use LVDS transmitters and receivers in the same I/O bank to clarify that the figures show connections that you need to make.
- Added topic about the CPA block under the Functional Description section. Moved information from the CPA feature guideline topic to this new topic.
- Updated the guideline topic about using the CPA feature to move information to a new CPA topic. Added link to the new topic.
- Updated the synthesizable design example topic to improve clarity and add duplex mode.
- Corrected the combined receiver and transmitter design example topic to specify that it creates an external PLL. The combined transmitter and receiver design example does not support the duplex feature.
- Updated the dynamic phase shift design example topic to specify that the design example does not support the duplex feature.
- Updated the LVDS SERDES IP core general settings reference topic to clarify the number of channels in the Duplex Feature mode and to update the CPA feature parameter name.
- Updated the names of the following IP cores:
- Intel FPGA LVDS SERDES to LVDS SERDES Intel FPGA IP
- Intel FPGA IOPLL to IOPLL Intel FPGA IP
- Intel FPGA GPIO to GPIO Intel FPGA IP