Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.3. Combined LVDS SERDES IP Core Transmitter and Receiver Design Example

The combined transmitter and receiver design example uses your LVDS SERDES IP core parameter settings and adds a complementary transmitter or receiver interface. Both interfaces are connected to the same external PLL. You can use the design example to see how to connect the transmitter and receiver interfaces.
Note: The combined transmitter and receiver design example does not support the duplex mode. If your LVDS SERDES IP core uses the Duplex Feature mode, ignore the ed_synth_tx_rx.qsys file generated by the Generate Example Design command.

If your LVDS SERDES IP core configuration implements a transmitter, the design example adds a DPA-FIFO receiver. If your LVDS SERDES IP core configuration implements any of the receiver interfaces, the design example adds a transmitter.

Figure 40. Combined LVDS SERDES Transmitter and Receiver


Generating and Using the Design Example

To generate the combined transmitter and receiver design example from the source files, run the following command in the design example directory:

quartus_sh -t make_qii_design.tcl -system ed_synth_tx_rx

The TCL script creates a qii_ed_synth_tx_rx directory that contains the ed_synth_tx_rx.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

For more information about make_qii_design.tcl arguments, run the following command:

quartus_sh -t make_qii_design.tcl -help

Did you find the information on this page useful?

Characters remaining:

Feedback Message