Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

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Document Table of Contents

1. Intel® Stratix® 10 High-Speed LVDS I/O Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.2
IP Version 20.0.0
The Intel® Stratix® 10 device family supports high-speed LVDS protocols through the LVDS I/O banks, the LVDS SERDES Intel® FPGA IP, and the GPIO Intel® FPGA IP.

Intel® Stratix® 10 devices support LVDS on all LVDS I/O banks:

  • All LVDS I/O banks support true LVDS input with RD OCT and true LVDS output buffer.
  • The devices do not support emulated LVDS channels.
  • The devices support true differential I/O reference clock for the I/O PLL that drives the serializer/deserializer (SERDES).
  • You can use each LVDS I/O pins pair as LVDS receiver or LVDS transmitter.
  • The LVDS SERDES IP core can place transmitter and receiver channels in the same I/O bank by using the Duplex Feature option.

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