Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

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4.3.3. Timing Analysis for the External PLL Mode

If you enable the Use external PLL parameter in the PLL Settings tab, the IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.

Some of the SERDES constraints are derived from the PLL clocks. Therefore, the external PLL clock settings must be generated before the LVDS SERDES IP core clock settings. In you project's .qsf, ensure that the line for the IOPLL IP core's .qip appears before the line for the LVDS SERDES IP core's .qip.

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