Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1. PLLs and Clocking for Intel® Stratix® 10 Devices

To generate the parallel clocks (rx_coreclock and tx_coreclock) and high-speed clocks (fast_clock), the Intel® Stratix® 10 devices provide I/O PLLs in the high-speed differential I/O receiver and transmitter channels.

Did you find the information on this page useful?

Characters remaining:

Feedback Message