Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

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3.1.6. Guideline: Pin Placement for Differential Channels

Each I/O bank contains its own PLL. The I/O bank PLL can drive all receiver and transmitter channels in the same bank, and transmitter channels in adjacent I/O banks. However, the I/O bank PLL cannot drive receiver channels in another I/O bank or transmitter channels in non-adjacent I/O banks.

Each PLL has its own dedicated reference clock input. You can use the dedicated reference clock input of a PLL in one bank to clock multiple PLLs that drive the LVDS channels in other banks. For example, you can use the dedicated reference clock input of bank 2A to clock the PLLs in banks 2B and 2C. If you share the reference clock source this way, you must manually promote the reference clock to the global clock network and ensure timing closure.

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