4.2.2. Initializing the LVDS SERDES IP Core in DPA Mode
Before the PLL lock is stable, use the rx_dpa_reset signal to keep the DPA in reset. When the DPA has determined the optimal phase tap, the rx_dpa_locked signal asserts. The LVDS SERDES IP core asserts the rx_dpa_locked port at the initial DPA lock. If you turn on the Enable DPA loss of lock on one change option, the rx_dpa_locked port deasserts after one phase change. If you turn off this option, the rx_dpa_locked signal deasserts after two phase changes in the same direction.
Intel recommends that you follow these steps to initialize and reset the LVDS SERDES IP core in DPA mode:
- During entry into user mode, assert the pll_areset and rx_dpa_reset signals. Keep the pll_areset signal asserted for at least 10 ns.
You can also perform this step at any time in user mode operation to reset the interface.
- After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
- Deassert the rx_dpa_reset port after the pll_locked port becomes asserted and stable.
- Apply the DPA training pattern and allow the DPA circuit to lock.
If a training pattern is not available, any data with transitions is required to allow the DPA to lock. For the DPA lock time specification, refer to the related information.
- After the rx_dpa_locked signal asserts, assert the rx_fifo_reset signal for at least one parallel clock cycle.
- To start receiving data, deassert the rx_fifo_reset signal.
During normal operation, every time the DPA shifts the phase taps to track variations between the reference clock source and the data, the data transfer timing margin between clock domains is reduced.
After the initialization, you can proceed to align the word boundaries (bitslip).
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