Intel® Stratix® 10 High-Speed LVDS I/O User Guide

ID 683792
Date 7/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.1. Initializing the LVDS SERDES IP Core in Non-DPA Mode

The PLL is operational after it achieves lock in user mode. Before transferring data using SERDES block with the LVDS SERDES IP core, ensure that the PLL is locked to the reference clock.

Intel recommends that you follow these steps to initialize the LVDS SERDES IP core in non-DPA mode:

  1. During entry into user mode, assert the pll_areset signal for at least 10 ns.
    You can also perform this step at any time in user mode operation to reset the interface.
  2. After at least 10 ns, deassert the pll_areset signal and monitor the pll_locked port.
After the PLL lock port asserts and becomes stable, the SERDES blocks are ready for operation.
After the initialization, you can proceed to align the word boundaries (bitslip).

Did you find the information on this page useful?

Characters remaining:

Feedback Message