AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents SLEW

Equivalent to the SLEW constraint in the Xilinx* Vivado* software, the SLEW_RATE logic option helps to reduce switching noise by controlling low-to-high or high-to-low transitions on output pins. When a large number of output pins switch simultaneously, pins that use the lower SLEW_RATE option help reduce switching noise. This option is only applicable to output or bidirectional pins.

The following example shows how to set the equivalent SLEW constraint to the output “q1”.

Example of XDC command:

# set fast slew rate to q1
set_property SLEW FAST [get_ports q1]

Equivalent QSF command:

# set programmable slew rate to q1
set_instance_assignment -name SLEW_RATE 1 -to q1

For more information about the slew rate feature in the device, refer to the specific device handbook.