AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents Hyper-Aware Design Flow

Use the Hyper-Aware design flow to shorten design cycles and optimize performance for designs targeting Intel® Stratix® 10 devices. The Hyper-Aware design flow combines automated register retiming (Hyper-Retiming), with implementation of targeted timing closure recommendations (Fast Forward compilation), to maximize use of Hyper-Registers and drive the highest performance for Intel® Stratix® 10 designs.