AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL)

Similar to Mixed-Mode Clock Managers (MMCM) in Xilinx* devices, some Intel® FPGA device families support PLLs. This ability increases device and board-level performance by allowing you to minimize clock skew and clock delay and provide support for clock synthesis.

You can convert MMCMs to PLLs in Intel® FPGA devices with the IP Catalog/Parameter Editor by using the Intel® FPGA IOPLL IP core, which allows you to create custom PLLs targeting to Intel® FPGA devices.

Note: Intel® now refers to the ALTPLL IP Core as Intel® FPGA IOPLL IP core.

Xilinx* MMCMs require specific input buffers to feed into the source clock port; for example, IBUF, IBUFG, or BUFGMUX. In contrast, PLLs in Intel® FPGA devices do not require input buffers when using the IP Catalog/Parameter Editor.