AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents Create Timing Constraints with the Timing Analyzer GUI

To create timing constraints with the Timing Analyzer GUI:

  1. Create a timing netlist by clicking Netlist > Create Timing Netlist.
  2. Click File > New SDC File to open a new SDC file.
  3. From the Constraints menu, select the constraint you want to add..

    The selected constraint's dialog box opens, and allows you to set the constraint's parameters.

    Figure 5. Example: Create Clock Dialog Box
  4. Enter the values in the dialog box, and click Insert to insert the SDC command into the open SDC file.
  5. Save the updated SDC file.

The constraints are available on the Constraint menu are:

  • Create Clock
  • Create Generated Clock
  • Set Clock Latency
  • Set Clock Uncertainty
  • Set Clock Groups
  • Remove Clock
  • Set Input Delay
  • Set Output Delay
  • Derive PLL Clocks
  • Derive Clock Uncertainty
  • Set False Path
  • Set Multicycle Path
  • Set Maximum Delay
  • Set Minimum Delay
  • Set Net Delay