AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Signal Tap Logic Analyzer

The Vivado* software includes the Integrated Logic Analyzer (ILA) feature to debug post-implemented designs on a FPGA. Similarly, the Intel® Quartus® Prime provides the Signal Tap Logic Analyzer; a multiple-input, digital acquisition instrument that captures and stores signal activity from any internal device node or nodes. The Signal Tap Logic Analyzer helps debug an FPGA design by probing the state of the internal signals in the design without using external equipment.
Table 27.   Signal Tap Logic Analyzer Features and Usage
Features Typical Usage
  • Uses FPGA resources.
  • Samples test nodes, and outputs the information to the Intel® Quartus® Prime software for display and analysis.
You have spare on-chip memory and you want functional verification of a design running in hardware.