AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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3.3.7. Finalize Pinout

In the Vivado* software, you can use the I/O Planning View Layout to finalize the pinout. For I/O planning of Memory Interfaces, the Vivado* software uses the Memory Bank/Byte Planner.

Intel® Quartus® Prime Pro Edition Software provides the Interface Planner and the Pin Planner to help you with the I/O Planning.

Table 17.  Finalize Pinout Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Finalize Pinout

Byte Planner for memory banks

Device Window and Package Window in I/O Planning View Layout

Interface Planner

Pin Planner