AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents Schematic/Block Editor

In the Intel® Quartus® Prime Pro Edition software, you can use Intel® FPGA-supplied design elements, such as Boolean gates and registers, or you can create your own symbols from HDL or EDA netlist design entities.
  • To create a block design file from a VHDL or Verilog HDL design file, click File > Create/Update, and click Create Symbol Files for Current File.
  • To create a new schematic file (*.bdf) in the Intel® Quartus® Prime Pro Edition software, point to File > New and select the Block Diagram/Schematic File.
  • To insert block symbols into the schematic, double-click the schematic file and choose the appropriate block symbols.
Figure 3. Schematic File