AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Determining Memory Block and Mapping Ports

  1. If you are not sure which memory block to select, or are not particular about the memory block type, select AUTO in the IP Catalog/Parameter Editor.
    This option allows the Intel® Quartus® Prime software to determine the memory block type at compile time.
    • To find the type of memory block that the Intel® Quartus® Prime software assigned to your design, check the Intel® Quartus® Prime Fitter RAM Summary Report.
  2. Otherwise, build the memory blocks in the IP Catalog/Parameter Editor using the proper plug-in.
    The available plug-ins are:
    Table 45.  Memory Modes/Functions and Related Plug-In
    Memory Modes/Function Plug-In
    Single-port RAM RAM:1-PORT
    Simple dual-port RAM RAM:2-PORT
    True dual-port RAM RAM:2-PORT
    Simple quad-port RAM ( Intel® Stratix® 10 only) RAM:4-PORT
    Single-port ROM ROM:1-PORT
    Dual-port ROM ROM:2-PORT

    For information about memory options, and how to build the memory function through the IP Catalog/Parameter Editor, refer to the embedded memory user guide.

  3. Identify the port-mapping from Xilinx* memory ports to Intel® FPGA memory ports.