AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents RTL Viewer

To run the RTL Viewer for an Intel® Quartus® Prime Pro Edition project:
  1. Click Processing > Start > Start Analysis & Elaboration to generate a RTL netlist
  2. To open the RTL Viewer, click Tools > Netlist Viewers (RTL Viewer).

Alternatively, you can perform a full compilation on any Intel® Quartus® Prime Pro Edition flow that includes the initial Analysis and Elaboration stage.