AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents Rapid Recompile

In Xilinx* Vivado* designs, the Incremental Compile design flow speeds up place and route runtime. For reduced compilation time, the Intel® Quartus® Prime Pro Edition provides Rapid Recompile.

During Rapid Recompile, the Intel® Quartus® Prime Pro Edition Compiler reuses previous synthesis and fitting results whenever possible, and does not reprocess unchanged design blocks. Use Rapid Recompile to reduce timing variations and the total recompilation time after making small design changes.
Note: Intel® Stratix® 10 devices support Rapid Recompile only for the Signal Tap Logic Analyzer.
To start Rapid Recompile following an initial compilation (or after running the Route stage of the Fitter), click Processing > Start > Start Rapid Recompile.