AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents write_sdf/write_verilog/write_vhdl

In Vivado* , the write_sdf executable reads data from design files, and writes timing delays in .sdf files. The write_verilog executable uses this output and generates the netlists for third-party tools. Similarly, the Intel® Quartus® Prime Pro Edition software provides the quartus_eda executable to generate netlists and other output files for use with third-party EDA tools.

The following example creates the filtref.vo simulation Verilog HDL netlist file, that you can use to simulate the filtref project with ModelSim* :

quartus_eda filtref --simulation=on --format=verilog --tool=modelsim

For command line help, type quartus_eda --help at the command prompt.