AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents Other Intel® FPGA Debugging Tools

These Intel® FPGA tools do not have a Xilinx* tools to compare with.

Signal Probe

Table 31.   Signal Probe Features and Usage
Features Typical Usage
Incrementally routes internal signals to I/O pins while preserving results from the last place-and-routed design. You have spare I/O pins and you want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope.

Logic Analyzer Interface

Table 32.  Logic Analyzer Interface Features and Usage
Features Typical Usage
  • Multiplexes a larger set of signals to a smaller number of spare I/O pins.
  • Allows you to select which signals switch onto the I/O pins over a JTAG connection.
You have limited on-chip memory and a large set of internal data buses to verify using an external logic analyzer. Logic analyzer vendors, such as Tektronics* and Agilent*, provide integration with the tool to improve usability.

In-System Memory Content Editor

Table 33.  In-System Memory Content Editor Features and Usage
Features Typical Usage
Displays and allows you to edit on-chip memory.

You want to view and edit the contents of on-chip memory that is not connected to a Nios® II processor.

You can also use the tool when you do not want to have a Nios® II debug core in your system.