AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents

3.3.16. Techniques to Improve Productivity

Table 36.  Techniques to Improve Productivity Comparison
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Techniques to improve productivity Incremental Compile Rapid Recompile20
Hierarchical Design Block-Based Design Flows
- Design Space Explorer II (DSE)
20 Rapid Recompile available only for Intel® Arria® 10 devices.