AN 307: Intel® FPGA Design Flow for Xilinx* Users

ID 683562
Date 3/20/2018

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Document Table of Contents

3.3. FPGA Design Flow Using Tools with GUIs

The Intel® Quartus® Prime Pro Edition and the Vivado* software GUIs address the major FPGA design steps in different ways.

Table 8.  GUI Feature Equivalents
GUI Feature Xilinx* Vivado* Software Intel® Quartus® Prime Pro Edition Software
Project Creation New Project New Project Wizard
Design Entry HDL Editor HDL Editor
EDA Netlist EDA Netlist
- Schematic/Block Editor
- State Machine Editor
IP Catalog IP Catalog and Parameter Editor
IP Integrator Platform Designer System Integration Tool
IP Packager Platform Designer Component Editor
IP Status Report IP Status Upgrade IP Components
Design Constraints Device, Physical and Timing Constraints window

Assignment Editor,

Timing Analyzer Text Editor

Synthesis Synthesis Analysis and Synthesis
Third-Party EDA Synthesis Third-Party EDA Synthesis
Design Implementation Implementation Fitter (Plan, Early Place, Place, Route, Retime0 and Finalize)
Finalize Pinout

Byte Planner for memory banks

Device Window and Package Window in I/O Planning View Layout

Interface Planner

Pin Planner

Viewing and Editing Design Placement

Device Window (in I/O Planner View Layout)

Package Window (in I/O Planner View Layout)

Chip Planner
Static Timing Analysis Report Timing Timing Analyzer
Generation of Device Programming Files Hardware Manager Assembler
Power Analysis

Xilinx* Power Estimator (XPE)

Report Power

Early Power Estimation (EPE)

Power Analyzer

Simulation Vivado* Simulator ModelSim* - Intel® FPGA Starter Edition
Third-Party Simulation Tools Third-Party Simulation Tools
Hardware verification Hardware Manager System Console
Integrated Logic Analyzer (ILA) and System ILA IP Signal Tap Logic Analyzer
Xilinx* Virtual Input Output (VIO) In-System Sources and Probes
JTAG-to-AXI Master System Console
IBERT IP and Serial I/O Analyzer Tool Transceiver Toolkit
Memory Calibration Debug Tool

EMIF Debug Toolkit


Remote Debug using Xilinx* Virtual Cable (XVC) Remote Debug using existing TCP/IP connection

Signal Probe 14

In-System Memory Content Editor

Logic Analyzer Interface (LAI)

View Netlist

Schematic Window (Elaborated)

Schematic Window (Synthesized)

Schematic Window (Implemented)

RTL Viewer (Post Synthesis)

Technology Map Viewer (Post-Mapping)

Technology Map Viewer (Post-Fitting)

Fast Forward Viewer (Post-Fitting)

Design Optimization - Hyper-Aware Design Flow15
Physical Optimization Physical Synthesis Optimization
Techniques to improve productivity Incremental Compile Rapid Recompile16
Hierarchical Design Block-Based Design Flows
- Design Space Explorer II (DSE)
Partial Reconfiguration Yes Yes
Output Products Design Checkpoints Export Design Partitions
Add-On Development Tools Vivado* High-Level Synthesis High-Level Synthesis Compiler
13 Available only for Intel® Arria® 10 devices.
14 Signal Probe available only for Intel® Arria® 10 devices.
15 Hyper-Aware Design Flow available only for Intel® Stratix® 10 devices.
16 Rapid Recompile available only for Intel® Arria® 10 devices.