2.4. Intel® Agilex™ D-Series FPGAs and SoCs
Device | Logic Element (Thousands) |
M20K | MLAB | DSP | |||
---|---|---|---|---|---|---|---|
Count | Size (Mb) |
Count | Size (Mb) |
18×19 Multiplier | Peak INT8 (TOPS 36 ) |
||
AGD 010 | 103 | 534 | 10.43 | 1,780 | 1.09 | 552 | 8.48 |
AGD 025 | 254 | 1,281 | 25.02 | 3,420 | 2.09 | 1,472 | 22.61 |
AGD 031 | 318 | 1,602 | 31.29 | 5,400 | 3.30 | 1,840 | 28.26 |
AGD 051 | 515 | 2.563 | 50.06 | 8,440 | 5.15 | 2,944 | 45.22 |
AGD 064 | 644 | 3,204 | 62.58 | 10,920 | 6.67 | 3,680 | 56.22 |
Device | HVIO (1.8 V–3.3 V) |
HSIO (1.05 V–1.3 V) |
PLL Count | 1.3 V LVDS Pairs at 1.6 Gbps |
External Memory | MIPI* D-PHY* Interface |
||
---|---|---|---|---|---|---|---|---|
I/O PLL | Fabric-Feeding I/O PLL37 | DDR4 |
DDR5 LPDDR4 LPDDR5 |
|||||
AGD 010 | 60 | 384 | 8 | 9 | 192 | 2×64 bit | 4×32 bit | 32 |
AGD 025 | 60 | 384 | 8 | 9 | 192 | 2×64 bit | 4×32 bit | 32 |
AGD 031 | 60 | 384 | 8 | 9 | 192 | 2×64 bit | 4×32 bit | 32 |
AGD 051 | 60 | 384 | 8 | 11 | 192 | 2×64 bit | 4×32 bit | 32 |
AGD 064 | 60 | 384 | 8 | 11 | 192 | 2×64 bit | 4×32 bit | 32 |
Device | Transceiver 28.1 Gbps Max. Rate |
PCIe 4.0 Hard IP |
25 Gigabit Ethernet (MAC & PCS) |
HPS | ||
---|---|---|---|---|---|---|
×4 | ×8 | Processor | Cache Size | |||
AGD 010 | 16 | 4 | 2 | 8 |
|
Shared:
Cortex* -A76:
Cortex* -A55:
|
AGD 025 | 16 | 4 | 2 | 8 | ||
AGD 031 | 16 | 4 | 2 | 8 | ||
AGD 051 | 24 | 6 | 3 | 12 | ||
AGD 064 | 32 | 8 | 4 | 16 |
Device | Package (Grid Array: Balls Anywhere) |
|||||||
---|---|---|---|---|---|---|---|---|
B082 820-pin BBGA38 (23 mm × 23 mm) 0.65 mm pitch |
B160 1596-pin BBGA38 (32 mm × 32 mm) 0.65 mm pitch |
|||||||
HVIO | HSIO | LVDS | Transceiver | HVIO | HSIO | LVDS | Transceiver | |
AGD 010 | 60 | 192 | 96 | 8 | 60 | 384 | 192 | 16 |
AGD 025 | 60 | 192 | 96 | 8 | 60 | 384 | 192 | 16 |
AGD 031 | 60 | 192 | 96 | 8 | 60 | 384 | 192 | 16 |
AGD 051 | — | — | — | — | 60 | 384 | 192 | 24 |
AGD 064 | — | — | — | — | 60 | 384 | 192 | 32 |
36 Tera Operations Per Second
37 The fabric-feeding I/O PLL counts include the System PLL in the transceiver banks. You can use the System PLL for core fabric usage if you do not use it for the transceiver.
38 Balls Anywhere Ball Grid Array