Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

2.4. Intel® Agilex™ D-Series FPGAs and SoCs

Table 18.   Intel® Agilex™ D-Series Device Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device

Logic Element

(Thousands)

M20K MLAB DSP
Count

Size (Mb)

Count

Size (Mb)

18×19 Multiplier

Peak INT8

(TOPS 36 )

AGD 010 103 534 10.43 1,780 1.09 552 8.48
AGD 025 254 1,281 25.02 3,420 2.09 1,472 22.61
AGD 031 318 1,602 31.29 5,400 3.30 1,840 28.26
AGD 051 515 2.563 50.06 8,440 5.15 2,944 45.22
AGD 064 644 3,204 62.58 10,920 6.67 3,680 56.22
Table 19.   Intel® Agilex™ D-Series Device Family Plan—I/Os and InterfacesThe values in this table are maximum resources or performance.
Device

HVIO

(1.8 V3.3 V)

HSIO

(1.05 V1.3 V)

PLL Count

1.3 V LVDS Pairs

at 1.6 Gbps

External Memory

MIPI*

D-PHY* Interface

I/O PLL Fabric-Feeding I/O PLL37

DDR4

DDR5

LPDDR4

LPDDR5

AGD 010 60 384 8 9 192 2×64 bit 4×32 bit 32
AGD 025 60 384 8 9 192 2×64 bit 4×32 bit 32
AGD 031 60 384 8 9 192 2×64 bit 4×32 bit 32
AGD 051 60 384 8 11 192 2×64 bit 4×32 bit 32
AGD 064 60 384 8 11 192 2×64 bit 4×32 bit 32
Table 20.   Intel® Agilex™ D-Series Device Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

Transceiver

28.1 Gbps Max. Rate

PCIe 4.0 Hard IP

25 Gigabit

Ethernet

(MAC & PCS)

HPS
×4 ×8 Processor Cache Size
AGD 010 16 4 2 8
  • Dual core Arm* Cortex* -A76 up to 1.8 GHz
  • Dual core Arm* Cortex* -A55 up to 1.5 GHz

Shared:

  • 2 MB L3

Cortex* -A76:

  • 64 KB L1
  • 256 KB L2

Cortex* -A55:

  • 32 KB L1
  • 128 KB L2
AGD 025 16 4 2 8
AGD 031 16 4 2 8
AGD 051 24 6 3 12
AGD 064 32 8 4 16
Table 21.   Intel® Agilex™ D-Series PackagesAll product lines are migratable within the same package. To achieve full migration across product lines in the same package, restrict transceivers utilization to match the product line with the lowest transceiver count.
Device Package

(Grid Array: Balls Anywhere)

B082

820-pin BBGA38

(23 mm × 23 mm)

0.65 mm pitch

B160

1596-pin BBGA38

(32 mm × 32 mm)

0.65 mm pitch

HVIO HSIO LVDS Transceiver HVIO HSIO LVDS Transceiver
AGD 010 60 192 96 8 60 384 192 16
AGD 025 60 192 96 8 60 384 192 16
AGD 031 60 192 96 8 60 384 192 16
AGD 051 60 384 192 24
AGD 064 60 384 192 32
36 Tera Operations Per Second
37 The fabric-feeding I/O PLL counts include the System PLL in the transceiver banks. You can use the System PLL for core fabric usage if you do not use it for the transceiver.
38 Balls Anywhere Ball Grid Array

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