Intel® Agilex™ 7 FPGAs and SoCs Device Overview

Download
ID 683458
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs 2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs 18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs 20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs 21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs 22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Intel® Agilex™ 7 FPGAs and SoCs 1.2. Intel® Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Intel® Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Intel® Agilex™ 7 SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Intel® Agilex™ 7 FPGAs and SoCs F-Series 2.2. Intel® Agilex™ 7 FPGAs and SoCs I-Series 2.3. Intel® Agilex™ 7 FPGAs and SoCs M-Series 2.4. Available Options
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Intel® Agilex™ 7 FPGAs and SoCs
2. Intel® Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel® Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Intel® Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Intel® Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Intel® Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Intel® Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Intel® Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Intel® Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Intel® Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Intel® Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Intel® Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Intel® Agilex™ 7 FPGAs and SoCs
18. Device Security for Intel® Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Intel® Agilex™ 7 FPGAs and SoCs
20. Power Management for Intel® Agilex™ 7 FPGAs and SoCs
21. Intel® Software and Tools for Intel® Agilex™ 7 FPGAs and SoCs
22. Revision History for the Intel® Agilex™ 7 FPGAs and SoCs Device Overview

16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs

The Intel® Agilex™ D-Series FPGA and SoC packages use the "balls anywhere" package design.

Compared to the standard ball grid array (BGA) packages, the "balls anywhere" package has a mixed ball pitch and differently-sized pads. The "balls anywhere" package has a mixed ball pitch size with a minimum ball pitch of 0.65 mm.

Figure 19. Comparison Between Standard Grid and Balls Anywhere


The mixed ball pitch helps reduce the package form factor by 1 mm to 2 mm. Despite the smaller package size, the "balls anywhere" packages can provide the same I/O pin count and compatible electrical performance compared to the standard BGA packages.

As shown in the following figure, the mixed ball grid pattern has differently-sized pads. This feature eases trace routability, reducing the design complexity, number of PCB layers, and board thickness and size—ultimately, reducing board cost and development time.

Figure 20. Example of PCB Trace Routing for Balls Anywhere Package


Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message