DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.28. Variable Integer Rate Decimation Filter

The variable integer rate decimation filter reference design implements a 16-channel interpolate-by-2 symmetrical 49-tap FIR filter. The target system clock frequency is 320 MHz.

You can modify the parameters in the setup_vardecimator_rt.m file, which you access from the Edit Params icon.

The model file is vardecimator_rt.mdl.