DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022

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Document Table of Contents

7.1.1. Scale

This design example demonstrates the Scale block.

The testbench allows you to see a vectorized block in action. Displays in the testbench track the smallest and largest values to be scaled and verify the correct behavior of the saturation modes.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus a ChanView block that deserializes the output bus.

The ScaleSystem subsystem includes the Device and Scale blocks.

The model file is demo_scale.mdl.