DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.4. Scaling with Primitive Blocks

Use Primitive library blocks to build your own run-time reconfigurable scaling.

Procedure

  1. Use the left shift operation to remove redundant MSBs; use bit extract to remove LSBs and preserve the MSBs.
  2. Choose the number of MSBs to discard with the run-time reconfigurable parameter that comes from an input port.
  3. Use a control register to connect to this port, and update the shift value by a processor such as a Nios II processor.
  4. If the FPGA clock is low, use this implementation to realize different scaling for different channels. If it is a high speed application and your processor bus updates much slower than logic clock rate, you cannot use this circuit to apply different scaling for different channels.